Present day digital circuit applications often involve analog-to-digital data converters (ADCs), which includes sampling circuitry that samples an analog input signal at points in time, and then converts the samples to digital values to create a digital signal. The use of ADCs is common for certain types of applications, which can involve receiving an input signal or input data represented by an analog signal, and then converting the analog signal to a digital signal for further processing by a logic block in a digital form. To provide the samples to the logic block, a serialized interface according to a format is often used. Specifically, data samples are organized as frames according to the serialized interface, and the frames are transmitted serially over one or more lanes to a logic block. In one example, a transmitter is provided with a framer, which interfaces between (analog-to-digital) data converters and a logic block.
One example of a serialized interface is the JESD204x series of standards, which defines a serialized interface between data converters and logic devices, written by the JEDEC Solid State Technology Association. For instance, the JESDC Solid State Technology Association has written a JESD204A standard in April 2008, and a JESD204B standard in July 2011. The JESD204B standard in particular defines a large range of possible specifications for a serial link (e.g., having different number of data converters, sample resolutions, and number of lanes). Furthermore, the standard defines a framing protocol for a range of specifications having different frame sizes and samples per frame.
Each application may have a different specification, where a particular specification may include a particular number of data converters, a particular number of links available for the logic block, a particular number of bits per converter, a particular number of samples per converter per frame, etc. Depending on the application, a designer would design circuits for the framer specific to the specification. The design process is time consuming and difficult. Moreover, the designer should have an in depth knowledge of the serialized interface and the format that the interface uses to design a suitable circuit.